Semiconductor switches and switching circuits for microwave

ABSTRACT

The purpose of the present invention is to provide a small-sized switch attaining high isolation of not less than 80 dB, maintaining low insertion loss also in high frequencies not less than 60 GHz. A semiconductor switch according to the present invention utilizes FETs a gate electrode, a source electrode, and a drain electrode of each of which are formed on a semiconductor. The source electrode and the drain electrode are connected with the earth as well as are disposed in parallel to each other, and the gate electrode is formed between the source electrode and the drain electrode, and both the ends of the gate electrode are connected to the first input-output terminal  1  and the second input-output terminal.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to semiconductor switches, and in particular tosemiconductor switches for microwave as well as millimeter wave bandsusing a transmission line comprising a dielectric substance substrateand metal conductors, and diodes or field effect transistors (FETs)showing distributed parameter effect.

2. Description of the Prior Art

As a semiconductor switching circuit which is contemplated for use inmicrowave as well as millimeter wave bands, in particular with highfrequencies not less than 60 GHz, various kinds of circuits have beenproposed and manufactured for trial.

Single-pole 3-throw (SP3T) switches for the 77 GHz band (hereinafter tobe referred to as Conventional example 1) were reported by M. Case etal. in “1997 MTT-S IMS Digest pp. 1047-1050” and can be nominated as anexample of conventional switches.

An SP3T switch of Conventional example 1 comprises configuration asshown in FIG. 12. An input terminal 20 is connected with a signaljunction N via a transmission line 21. One end of each transmission line22-24 having length of a quarter of propagating wave length (a quarterwave length transmission line) is connected via capacitance C1, C2, andC3 for DC cutting respectively to each signal junction. The other end ofeach of a quarter wave length transmission lines 22-24 is connectedrespectively to one end of PIN diode D1, D2, or D3 as well as to thefirst, the second, or third output terminal 25-27. The other end of eachPIN diode D1, D2, or D3 is connected with the earth. Capacitance C1, C2,and C3 for DC cutting, a quarter wave length transmission lines 22-24,diodes D1, D2, and D3, and the first, the second, and the third outputterminals 25-27 form three output signal passes.

A diode can be expressed as a resistance for equivalent circuit thereofwhen the diode is biased forward, and can be expressed as a capacitancefor equivalent circuit thereof when the diode is biased in the reversedirection. Accordingly, when a diode is biased forward, there existslittle impedance, and the anode and cathode thereof may be regarded tobe short-circuited. In addition, the impedance for frequencies incorrespondence with propagating wave length when this diode is seen viaa quarter wave length transmission line is close to infinite, and thusmay be regarded as almost open. That is, a signal pass where a diode isbiased forward will be seen as almost open from the signal junction, andas a consequence, an RF signal having propagated the signal pass will bealmost totally reflected. On the other hand, since a diode which isbiased in the reverse direction functions as a capacitance, theimpedance will get high for low frequencies, and accordingly a signalpass where a diode is biased in the reverse direction is transparent. Asthe frequency gets higher, the impedance of a capacitance gets lower,and therefore, signal reflection at a signal junction will increase. Asa result, a signal pass where a diode is biased in the reverse directionallows signals to travel transparently, but on the other hand, anincrease in frequency will result in an increase in loss due toreflection.

Thus, in switches of Conventional example 1, among the three outputsignal passes, the signal pass to make signals travel transparentlycomprises a diode, which is biased in the reverse direction, and on theother hand, the other remaining signal passes comprise diodes, which arebiased forward, to cut off signals on the other remaining signal passes,which will enable to switch the signal passes.

Insertion loss as well as isolation in a single-pole single-throw (SPST)of Conventional example 1 as described above can for the purpose ofsimplicity be supposed that characteristic impedance of the transmissionline equals impedance of the input-output terminals, and then can beexpressed as the equation (1) and the equation (2). $\begin{matrix}{{IL} = \frac{4}{4 + {\omega^{2}C^{2}Z_{0}^{2}}}} & (1) \\{I_{SO} = \frac{4}{\left( {2 + \frac{Z_{0}}{R}} \right)}} & (2)\end{matrix}$

As apparent from the equation (2), isolation is expressed with theresistance R and the impedance Z₀ of the input-output terminals, butdoes not depend on frequencies. In switches of Conventional example 1,however, when isolation of, for example, not less than 40 dB is to beattained, the resistance values of diode will have to be not more than0.13 Ω. Here, in the disclosed document of Conventional example 1, theresistance value of the diode is described as 3 Ω. Accordingly, inswitches of Conventional example 1, for the purpose of realizing aresistance value of 0.13 Ω, the anode electrode area to be multipliedapproximately by 23 will do. However, the anode electrode area being 23times as much means that the capacitance value will simultaneously be 23times as much as well. As a result, since the capacitance value of thediode disclosed in the document is 33 fF, the capacitance to attainisolation of 40 dB will be 759 fF which is 23 times as much. Based onthis, with reference to the equation (1), insertion loss for acapacitance of 33 fF (=33×10⁻¹⁵ F) is 0.6 dB, while insertion lossreaches as much as 19 dB when the anode electrode area is made 23 timesas much. That is, in switching circuit of the above-describedConventional example 1, insertion loss and isolation are in a trade-offrelationship, and high isolation characteristics such as 40 dB were notattainable.

In addition, single-pole single-throw (SPST) switches for the 94 GHzband (hereinafter to be referred to as Conventional example 2) werereported by H. Takasu et al. in “IEEE MICROWAVE AND GUIDED LETTERS, Vol.6, pp. 315-316” and can be nominated, conventionally, as an example ofanother switch. This switch of Conventional example 2 is also one ofpossible circuits as switching circuits for high frequency bands notless than 60 GHz.

An SPST switch of Conventional example 2 comprises configuration asshown in FIG. 13. An SPST switch of Conventional example 2 comprises afield effect transistor (FET), an inductor, and a resistance. Theinput-output terminals 31, 32 are respectively connected with the sourceand drain of an FET, between which an inductor L configured with amicrostrip line pass is connected in parallel. To the gate of FET, aresistance R of 2.5 kΩ is connected, and via the resistance a directcurrent bias is arranged to be applied to the gate. In the state thatthe channel of FET is closed, the FET can be treated equivalently as acapacitance C, which, therefore, as shown in FIG. 14, together with theinductance L connected with the FET in parallel, resonance takes placeat a frequency obtainable from the equation (3), and as a consequence,resulting in high impedance so that signal propagation between theinput-output terminals will be cut off. That is, the switch enters theoff state. $\begin{matrix}{f = \frac{1}{2\pi\sqrt{LC}}} & (3)\end{matrix}$

FIG. 15 shows frequency characteristics on insertion loss as well asisolation in the switch of Conventional example 2. As obvious from FIG.15, in the switching circuit of Conventional example 2, isolationcharacteristics around 30 dB are attainable with comparatively lowinsertion loss. However, since, as described before, the switchingcircuit of Conventional example 2 makes use of resonance, its frequencycharacteristics will fall in narrow band width. Moreover, for thepurpose of making a resonance circuit start resonance at a desiredfrequency, it is necessary to accurately know LC being a constant of thecircuit. Accordingly, for the purpose of using a switch of Conventionalexample 2, not only the capacitance C to appear at closure of the FETchannel will have to be accurately estimated, but also as concerns theinductor L accurate modeling will become necessary. On the contrary,FETs as well as PIN diodes, etc., normally have variation of formingprocess to a certain extent, but for example, due to this variation, thevalue of capacitance C could deviate from the design, and as a resultthe resonance frequency will deviate from the design as well, andresonance will not be available at a desired frequency, which, as aconsequence, will give rise to reduction of yield.

Switching circuits (hereinafter to be referred to as Conventionalexample 3) were conventionally proposed by H. Mizutani and Y. Takayamain “1997 MTT-S IMS Digest pp. 439-442” and can be nominated astechnology to solve the problems with the aforementioned Conventionalexample 1 as well as Conventional example 2. The switching circuit ofConventional example 3 is a switching circuit utilizing an FET showingdistributed parameter effect, and its wide band width characteristicswere proved in the document. Incidentally, the contents of the documenthas been disclosed in Japanese Patent Laid-Open No. 10-41404specification as well.

A switching circuit of Conventional example 3 comprises theconfiguration as shown in FIG. 16. As understandable with reference toFIG. 16, the switching circuit of Conventional example 3 comprisesplural transmission lines and plural FETS. For the switching circuit ofConventional example 3 in detail, each transmission line as well as eachFET is respectively defined per micro unit length, and transmissionlines are connected in series, and the drain of each FET is connected tothe respective junction of them. Incidentally, the source of each FET isconnected with the earth. The configuration is made in an infiniteconnection of these transmission line as well as FET per micro unitlength.

Such switching circuit of Conventional example 3 is implemented as aplane surface pattern, where each FET (hereinafter to be referred to asdistributed parameter FET) comprises a source connected with the earth,a gate finger with a length of 400 μm, and a drain electrode, bothlongitudinal ends of which have been connected with the input-outputterminals.

A switching circuit of Conventional example 3 comprising such aconfiguration acts equivalently as a transmission line without any lossas shown in FIG. 17 in the state that the channel of FET is closed. Asapparent from FIG. 17, the switch enters the ON state, and insertionloss is expressed by the equation (4) through the equation (6).$\begin{matrix}{S_{21}^{ON} = \frac{2{ZZ}_{0}}{{2{ZZ}_{0}\cos\quad{\beta 1}} + {j\quad\left( {Z^{2} + Z_{0}^{2}} \right)\quad\sin\quad{\beta 1}}}} & (4) \\{\beta = {\omega\sqrt{\left( {L\quad\left( {C_{IL} + C_{FET}} \right)} \right.}}} & (5) \\{Z = \sqrt{\frac{L}{\left( {C_{IL} + C_{FET}} \right)}}} & (6)\end{matrix}$

Here, “Z” represents impedance of the switch, “1” represents length of afinger of an FET, Z₀ represents impedance of the input-output terminal.In addition, “ω” represents angular frequency, and L, R, C, and Grespectively represent inductance, resistance, parallel capacitance,parallel conductance per unit length of the switch.

On the other hand, an FET is equivalently expressed as a mere resistancein the state where its channel is open, thus, the equivalent circuit onthe switch at that time will be as shown in FIG. 18. As understandablewith reference to FIG. 18, a switching circuit of Conventional example 3acts equivalently as a transmission line with loss in the state that thechannel of FET is open, that is, the switch enters the OFF state, andits isolation can be expressed by the equation (7) through the equation(9). $\begin{matrix}{S_{21}^{ON} = \frac{2{ZZ}_{0}}{{2{ZZ}_{0}\cosh\quad\psi} + {\left( {Z^{2} + Z_{0}^{2}} \right)\quad\sinh\quad\psi}}} & (7) \\{\gamma \equiv {\alpha + {j\beta}} \equiv \sqrt{{j\omega}\quad L\quad\left( {{{j\omega}\quad C_{IL}} + G} \right)}} & (8) \\{Z = \sqrt{\frac{{j\omega}\quad L}{{{j\omega}\quad C_{IL}} + G}}} & (9)\end{matrix}$

From these equations, in a wide band as shown in FIG. 19, low insertionloss and high isolation are obtainable. As understandable from FIG. 19,frequency characteristics of isolation in the switching circuit ofConventional example 3 are in gradual increase.

However, not only in switching circuits of the above-describedConventional example 1 as well as Conventional example 2 without doubt,but also in switching circuit of Conventional example 3 it waspractically difficult to maintain low insertion loss and realize highisolation in a wide band as a comparatively compact type. This point isexplained in detail as follows.

In a switch according to Conventional example 3, the 0^(th) digit termconcerning the frequency of isolation is expressed by the equation (10).$\begin{matrix}{{IL}_{DC} = \left( \frac{2}{2 + \frac{Z_{0}}{r}} \right)^{2}} & (10)\end{matrix}$

As understandable from the equation (10), as resistance “r” ofdistributed parameter FET gets smaller, isolation gets greater.Incidentally, in the switching circuit using a distributed parameterFET, the 0^(th) digit close resemblance on the isolation frequencycorresponds with the isolation of the switching circuit with shuntconfiguration using a lumped constant FET expressed in theaforementioned equation (2).

Accordingly, for the purpose of attaining high isolation in theswitching circuit of Conventional example 3, the gate finger length mustbe lengthened so that the resistance “r” of distributed parameter FET bereduced. In particular, for the purpose of attaining high isolation ofnot less than 80 dB in the switching circuit of Conventional example 3,the gate finger length must be lengthened to, for example, 1 mm so thatthe resistance “r” of distributed parameter FET be reduced. To extendthe gate finger length like this means the chip size of microwave ormillimeter wave single integrated circuit (MMIC) will get bigger.

As understandable from these features, in microwave or millimeter waveband switching circuits there was a problem that it was difficult forthe prior art to realize high isolation of not less than 80 dB coveringa wide band width with a comparatively small type configuration, whilemaintaining low insertion loss. This was originated in circuitconfigurations in the respective prior arts, such as, existencerespectively of the trade-off relationship between insertion loss andisolation, narrow band width characteristics due to usage of resonance,or the trade-off relationship between resistance of distributedparameter FET and the chip size.

BRIEF SUMMARY OF THE INVENTION OBJECT OF THE INVENTION

The present invention was made contemplating on those problems presentedby these prior arts, and in particular the purpose thereof is to providesmall-sized switching circuits for microwave or millimeter wave bandwhich can attain high isolation of not less than 80 dB covering a wideband width with a low loss, which the prior arts were hardly successfulin realizing in high frequencies not less than 60 GHz.

SUMMARY OF THE INVENTION

The present invention provides semiconductor switches and switchingcircuits shown as follows as means for solving the above-describedproblems.

Operation of semiconductor switches and switching circuits of thepresent invention comprising such configuration can be explained asfollows by exemplifying a first semiconductor switch as well as a thirdsemiconductor switch for example.

The first semiconductor switch as well as the third switch circuitaccording to the present invention functions as a coplanar line withoutany loss under the ON state, and functions as a coplanar line with lossunder the OFF state. On such points, these switches are similar to thoseswitching circuits of Conventional example 3. Accordingly, the insertionloss of switches according to the present invention is expressed by theaforementioned equations (4) through (6), and likewise isolation isexpressed by the equations (7) through (9). Moreover, in the switchesaccording to the present invention, isolation gradually increases onfrequency.

As described above, in the switching circuit functioning as a coplanarline without loss and with loss respectively in the ON state and in theOFF state, the 0^(th) digit close resemblance on the isolation frequencyis expressed by the equation (10). In addition, as being understood fromthis equation, larger isolation may be obtained by reducing theresistance “r”, which is as mentioned before.

Qualitatively, with a constant sheet resistance value, wider width of anelement reduces the resistance value, and longer length of an elementincreases the resistance value, which is generally known.

Here, with the width of an FET being constant, comparison between theswitching circuits of Conventional example 3 and semiconductor switchesand switching circuits according to the present invention leads to thefollowing understanding. That is, the resistance value of thedistributed parameter FET in Conventional example 3 is already definedby the source-drain distance. On the contrary, the resistance values ofthe resistance defining isolation in the switches according to thepresent invention depend on the gate-source, and the gate-draindistances. In detail, a switch according to the present inventioncomprises such a configuration that the source, the gate, and the drainof a so-called Schottky barrier FET are enclosed by an active layer, andthe source as well as the drain is connected with the earth. Thus, whenforward bias voltage which is to determine the current value to flow tothe gate by the source-drain resistance is supplied as gate voltage tobetween the gate and source as well as between the gate and the drain,the resistance which determines the isolation in the switches of thepresent invention is understood to be the source resistance between thegate and the source or the drain resistance between the gate and thedrain of Schottky barrier diode. That is, unlike Conventional example 3,in the switches according to the present invention, the resistance valueto determine isolation is determined by distances between gate andsource as well as between gate and drain. This leads to understandingthat the resistance value of the resistance to determine isolation inthe switches of the present invention is simply considered to bedecreased to approximately a half of that of Conventional example 3since the gate electrode of an FET to be used for switches is disposedin general in the middle between the source and the drain. Incidentally,for easier understanding, the contact resistance is set to be constant.As understandable from the foregoing, the semiconductor switchesaccording to the present invention can realize compactness as well aslower loss, and high isolation when compared with not only Conventionalexamples 1 and 2 but also Conventional example 3.

BRIEF DESCRIPTION OF THE DRAWINGS

This above-mentioned and other objects, features and advantages of thisinvention will become more apparent by reference to the followingdetailed description of the invention taken in conjunction with theaccompanying drawings, wherein:

FIG. 1A is a plan view showing a semiconductor switch according to afirst embodiment of the present invention and FIG. 1B is a crosssectional view taking along a line 1′ of FIG. 1A;

FIG. 2 is a circuit diagram showing a switching circuit equivalent tothe semiconductor switch according to the first embodiment of thepresent invention;

FIG. 3 is a graph showing frequency characteristics on insertion loss aswell as isolation of the semiconductor switch according to an example incorrespondence with the first embodiment of the present invention;

FIG. 4A is a plan view showing the semiconductor switch according to asecond embodiment of the present invention and FIG. 4B is a crosssectional view takng along a line 4′ of FIG. 4A;

FIG. 5 is a circuit diagram showing the switching circuit equivalent tothe semiconductor switch according to the second embodiment of thepresent invention;

FIG. 6 is a graph showing frequency characteristics on insertion loss aswell as isolation of the semiconductor switch according to an example incorrespondence with the second embodiment of the present invention,which is controlled by using only negative electric power;

FIG. 7 is a graph showing frequency characteristics on insertion loss aswell as isolation of the semiconductor switch according to an example incorrespondence with the second embodiment of the present invention,which was controlled by using both positive and negative electric power;

FIG. 8A is a plan view showing the semiconductor switch according to athird embodiment of the present invention and FIG. 8B is a crosssectional view taking along a line 8′ of FIG. 8A;

FIG. 9 is a circuit diagram showing the switching circuit equivalent tothe semiconductor switch according to the third embodiment of thepresent invention;

FIG. 10 is a graph showing frequency characteristics on insertion lossas well as isolation of the semiconductor switch according to oneexample in correspondence with the third embodiment of the presentinvention;

FIG. 11 is a graph showing frequency characteristics on insertion lossas well as isolation of the semiconductor switch according to anotherexample in correspondence with the third embodiment of the presentinvention;

FIG. 12 is a circuit diagram showing an SP3T switch of Conventionalexample 1;

FIG. 13 is a circuit diagram showing an SPST switch of Conventionalexample 2;

FIG. 14 is an equivalent circuit diagram showing an OFF state SPSTswitch of Conventional example 2;

FIG. 15 is a graph showing frequency characteristics on insertion lossas well as isolation of the SPST switch of Conventinal example 2;

FIG. 16 is an equivalent circuit diagram showing an SPST switch ofConventional example 3;

FIG. 17 is an equivalent circuit diagram showing an ON state SPST switchof Conventional example 3;

FIG. 18 is an equivalent circuit diagram showing an OFF state SPSTswitch of Conventional example 3; and

FIG. 19 is a graph showing frequency characteristics on insertion lossas well as isolation of the SPST switch of Conventinal example 3.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The semiconductor switch according to a first embodiment of the presentinvention comprises the configuration as shown in FIGS. 1A and 1B, andthe switching circuit according to the first embodiment of the presentinvention comprises the configuration as shown in FIG. 2.

With reference to FIG. 1, the semiconductor switch according to thepresent embodiment comprises the source electrode 4, drain electrode 5,and the gate electrode 6 which are enclosed by an active layer 3. Theseelectrodes are disposed in parallel to each other in a predetermineddirection on the semiconductor substrate (in this example, in theright-left lateral direction on the paper surface). The source electrode4 and the drain electrode 5 are respectively connected with-the earth,and the gate electrode 6 is disposed in between these source electrode 4and drain electrode 5. Both the ends of the gate electrode 6 in thepredetermined direction operate respectively as the first and the secondinput-output units, and are connected to the first input-output terminal1 and the second input-output terminal 2.

Circuit-wise, as shown in FIG. 2, this configuration is equivalent to aswitching circuit comprising the coplanar lines and field effecttransistors, wherein the first input-output terminal 1 is connected withone end of the signal line of the first coplanar line 9, and the gate ofthe first field effect transistor 10 is connected with the other end ofthe signal line of the first coplanar line 9, and the secondinput-output terminal 2 is connected with one end of the signal line ofthe second coplanar line 11, and the gate of the second field effecttransistor 12 is connected with the other end of the signal line of thesecond coplanar line 11, and further, to and between the first fieldeffect transistor 10 and the second field effect transistor 12 pluralcoplanar lines and plural field effect transistors are alternatelyconnected in series. Incidentally, in the present embodiment, eachcoplanar line comprises such a configuration that the signal line issandwiched by a grounded conductor, and each field effect transistor isa distributed parameter FET, and its source as well as its drain isconnected with the earth. Thus configured semiconductor switches andswitching circuits are mounted as a plane pattern where in thedistributed parameter FET the source electrode as well as the drainelectrode of which is connected with the earth the input-output terminalhas been connected with both the ends of the gate electrode disposed inthe longitudinal direction, and also can be easily formed by connectingthe source-drain electrodes of MESFET (metal-semiconductor field-effecttransistor) with the earth.

The semiconductor switch and the switching circuits comprising suchconfigurations are arranged so that positive voltage as well as zerobias is applied to the gate electrode 6 outside the active layer 3 by anot-shown bias line via a resistance. At this time, when required,capacitance C1, C2, and C3 for DC cutting is inserted between the gateelectrode 6 and each input-output terminal.

When positive voltage is applied to the gate electrode 6, and a currentflows into the gate electrode, forward bias is to be given to betweenthe gate and the source as well as between the gate and the drain, whichcan be regarded as short-circuited. At this time, a gate-source line aswell as a gate-drain line can respectively be equivalently expressed asa resistance, and accordingly, an equivalent circuit of the switch willbe a coplanar line with loss in shunt due to conductance. That is, theswitch enters the OFF state. The isolation characteristics under thisstate can be calculated by the aforementioned equations (7) through (9),using the conductance G of shunt.

On the other hand, in the case where zero bias is supplied to the gateelectrode 6, lines between the gate and the source as well as betweenthe gate and the drain can be regarded as open, and their equivalentcircuits can be expressed in capacitance. At this time, the switch isequivalently the same as circuit configuration of a coplanar linewithout loss, and enters the ON state.

Here, the semiconductor switch and the switching circuits according tothe present embodiment are partly characterized by low characteristicimpedance of the coplanar line due to shunt capacitance between the gateand the source as well as between the gate and the drain. Accordingly,mismatching between characteristic impedance and impedance of theinput-output terminal will give rise to reflection, and that reflectionwill give rise to insertion loss. This insertion loss can be calculatedby the aforementioned equations (4) through (6). With the semiconductorswitch and the switching circuits according to the present embodiment,switching between the ON state and the OFF state can be conducted by apositive electric power, which is additional characteristics.

For the purpose of cultivating better understanding on the presentembodiment, an example of the semiconductor switch and the switchingcircuits will be introduced hereunder, and explained in detail withreference to the drawings.

In the present example, a heterojunction FET of AlGaAs and InGaAssystems was used as the FET in the above-described first embodiment. Indetail, referring to FIG. 1B, a n-AlGaAs layer is formed on an i-GaAslayer. An i-InGaAs layer as a channel layer is formed on the n-AlGaAslayer. A n-AlGaAs layer is formed on the i-InGaAs layer. 2 n⁺-GaAslayers are formed on the n-AlGaAs layer apart from each other. The gateelectrode 6 is formed on the n-AlGaAs layer between the n⁺-GaAs layers.The gate electrode 6 is made by aluminum, gold, molybdenum, titanium, ortungsten silicide. The source electrode 4 is formed on one of then⁺-GaAs layer. The drain electrode 5 is formed on the other of then⁺-GaAs layer. The source and drain electrodes are made by an alloyincluding AuGe or nickel. In addition, the area of the gate electrode 6was set to 2×400 μm, and the distances between the gate electrode 6 andthe source electrode 4 or the drain electrode 5 were set to 2.5 μm.Moreover, the first input-output terminal 1 and the second input-outputterminal 2 are respectively connected with both the ends of the gateelectrode 6, and further, 50 Ω loads are respectively connected with thefirst input-output terminal 1 and the second input-output terminal 2.Incidentally, capacitance with zero bias between the gate and the sourceand between the gate and the drain is 20 fF per 100 μm, and on the otherhand, resistance with forward bias is 3.3 Ω per 100 μm. In addition,entire length of the coplanar line is 400 μm.

In the semiconductor switch according to the present example comprisingsuch configuration, 2 V and 0 V are applied to the gate so as toalternate the ON and OFF states. The principle of its operation is asdescribed before.

Frequency characteristics on insertion loss as well as isolation of thesemiconductor switch according to the present example are shown in FIG.3. As understandable with reference to FIG. 3, both show wide band widthcharacteristics, and insertion loss at 76.0 GHz is 1.7 dB, and isolationis 81 dB. That is, the semiconductor switch according to the presentexample is the one which has realized high isolation of not less than 80dB, maintaining low insertion loss, which was conventionally hardlysuccessful in realizing in high frequencies not less than 60 GHz. Sucheffects become obtainable since, as mentioned before, in the switch inthe OFF state conductance of shunt is twice as much as that in switchingcircuits according to the prior arts, that is, resistance is reduced byhalf. Incidentally, it goes without saying that the switch according tothe present example features its operability only by positive electricpower as described above.

The semiconductor switch according to a second embodiment of the presentinvention comprises the configuration as shown in FIGS. 4A and 4B, andthe switching circuit according to the second embodiment of the presentinvention comprises the configuration as shown in FIG. 5.

With reference to FIG. 4A, the semiconductor switch according to thepresent embodiment comprises the two anode electrodes 7, and the cathodeelectrode 8 which are enclosed by an active layer 3. From two anodeelectrodes 7, one together with the cathode electrode 8 forms a Schottkybarrier diode. In detail, referring to FIG. 4B, an i-AlGaAs layer isformed on an i-GaAs layer. An i-InGaAs layer as a channel layer isformed on the i-AlGaAs layer. A n-AlGaAs layer is formed on the i-InGaAslayer. The anode electrodes 7 are formed on the n-AlGaAs layer apartfrom each other. The cahorde electrode 8 is formed on the n-AlGaAs layerthrough a n⁺-GaAs layers. The anode electrode 7 are made by aluminum,gold, molybdenum, titanium, or tungsten silicide. The cathodelectrode ismade by an alloy including AuGe or nickel. In addition, the other anodeelectrode 7, likewise, together with the cathode electrode 8 may beconsidered to form a Schottky barrier diode, or may be considered to bean additional electrode established as an annex to the Schottky barrierdiode. Anyway the two anode electrodes 7 are both connected with theearth, and are disposed in parallel to each other in a predetermineddirection on the semiconductor substrate (in this example, in theright-left lateral direction on the paper surface). In addition, thecathode electrode 8 is disposed so as to be sandwiched between the twoanode electrodes 7 as well as, likewise, to be in parallel to each otherin a predetermined direction on the semiconductor substrate. The anodeelectrodes 7 have undergone Schottky junction with semiconductorcrystal, and the cathode electrode 8 has undergone ohmic junction withsemiconductor crystal. Both the ends of the cathode electrode 8 in thepredetermined direction operate respectively as the first input-outputunit and the second input-output unit, and are respectively connectedwith the first input-output terminal 1 and the second input-outputterminal 2. Such semiconductor switches are driven by supplying thecathode electrode 8 with negative voltage as well as zero bias outsidethe active layer 3 by a not-shown bias line via a resistance. At thistime, when required, capacitance C1, C2, and C3 for DC cutting isinserted between the cathode electrode 8 and each input-output terminal.

Circuit-wise, as shown in FIG. 5, this configuration is equivalent to aswitching circuit comprising the coplanar lines and diodes, wherein thefirst input-output terminal 1 is connected with one end of the signalline of the first coplanar line 9, and the cathode of the first diode 13is connected with the other end of the signal line of the first coplanarline 9, and the second input-output terminal 2 is connected with one endof the signal line of the second coplanar line 11, and the cathode ofthe second diode 14 is connected with the other end of the signal lineof the second coplanar line 11, and further, to and between the firstdiode 13 and the second diode 14 plural coplanar lines and plural diodesare alternately connected in series. Incidentally, in the presentembodiment, each coplanar line comprises such a configuration that thesignal line is sandwiched by the grounded conductor, and each diode is adistributed parameter diode, and its anode is connected with the earth.

For the purpose of cultivating a better understanding on the presentembodiment, an example of the semiconductor switch and the switchingcircuits will be introduced hereunder, and explained in detail withreference to the drawings.

In the present example, the area of the cathode electrode 8 was set to5×400 μm, and the distance between the cathode electrode 8 and the anodeelectrode 7 was set to 3 μm. In addition, the first input-outputterminal 1 and the second input-output terminal 2 are respectivelyconnected with both the ends of the cathode electrode 8, and further, 50Ω loads are respectively connected with the first input-output terminal1 and the second input-output terminal 2. Incidentally, capacitance withzero bias between the cathode and the anode is 20 fF per 100 μm, and onthe other hand, resistance with forward bias is 4 Ω per 100 μm. Inaddition, entire length of the coplanar line is 400 μm.

In the semiconductor switch according to the present example comprisingsuch configuration, negative voltage (−2 V for the present example), andzero bias are supplied to the cathode so as to alternate the states ofthe switch. That is, when negative voltage is applied to the cathode ofthe semiconductor switch according to the present example, forward biasis to be given to the diode, an equivalent circuit of which is expressedby resistance, thus the switch can be regarded as a coplanar line withloss in shunt due to conductance. That is, at this time, the switchenters the OFF state. On the other hand, when zero bias was supplied tothe cathode of the semiconductor switch according to the presentexample, an equivalent circuit of the diode is expressed by capacitance,thus the switch is equivalent to a coplanar line without loss.Accordingly, the switch enters the ON state.

Frequency characteristics on insertion loss as well as isolation of thesemiconductor switch according to the present example are shown in FIG.6. As understandable with reference to FIG. 6, both show wide band widthcharacteristics, and insertion loss at 110.0 GHz is 1.7 dB, andisolation is 82 dB. That is, it can be easily understood that thesemiconductor switch according to the present example is the one whichhas realized high isolation of not less than 80 dB, maintaining lowinsertion loss, which was conventionally hardly successful in realizingin high frequencies not less than 60 GHz.

Here, both of positive and negative electric power should be applicableto the cathode. In this case, the diode is to be biased in the oppositedirection when the positive voltage is 5 V, its capacity will decreasecompared with that at the time of zero bias. In addition, at this timethe switch is in the ON state, but the impedance of the switchapproaches 50 Ω and thus insertion loss gets lowered.

Frequency characteristics on insertion loss as well as isolation of thesemiconductor switch according to the present example in this case areshown in FIG. 7. As obvious with reference to FIG. 7, compared with thetime of zero bias, insertion loss is reduced to 1.5 dB at 110.0 GHz.Incidentally, as obvious from the aforementioned equations (7) through(9), isolation, which does not depend on capacitance of diodes, is 82dB, which remains same as in the time of zero bias without any changesto occur.

The semiconductor switch according to a third embodiment of the presentinvention comprises the configuration as shown in FIGS. 8A and 8B, andthe switching circuit according to the third embodiment of the presentinvention comprises the configuration as shown in FIG. 9.

With reference to FIG. 8, the semiconductor switch according to thepresent embodiment comprises two cathode electrodes 8, and the anodeelectrode 7 which are enclosed by an active layer 3. From two cathodeelectrodes 8, one together with the anode electrode 7 form a Schottkybarrier diode. In addition, the other cathode electrode 8, likewise,together with the anode electrode 7 may be considered to form a Schottkybarrier diode, or may be considered to be an additional electrodeestablished as an annex to the Schottky barrier diode. Anyway the twocathode electrodes 8 are both connected with the earth, and are disposedin parallel to each other in a predetermined direction on thesemiconductor substrate (in this example, in the right-left lateraldirection on the paper surface). In addition, the anode electrode 7 isdisposed so as to be sandwiched between the two cathode electrodes 8 aswell as, likewise, to be in parallel to each other in a predetermineddirection on the semiconductor substrate. The anode electrode 7 hasundergone Schottky junction with semiconductor crystal, and the cathodeelectrodes 8 have undergone ohmic junction with semiconductor crystal.In detail, referring to FIG. 8B, an i-AlGaAs layer is formed on ani-GaAs layer. An i-InGaAs layer as a channel layer is formed on thei-AlGaAs layer. A n-AlGaAs layer is formed on the i-InGaAs layer. Thecathodelectrodes 8 are formed on the n-AlGaAs layer apart from eachother through the respective n⁺-GaAs layer. The anode electrode 7 isformed on the n-AlGaAs layer. The anode electrode 7 is made by aluminum,gold, molybdenum, titanium, or tungsten silicide. The cathodelectrodes 8are made by an alloy including AuGe or nickel. Both the ends of theanode electrode 7 in the predetermined direction operate respectively asthe first input-output unit and the second input-output unit, and arerespectively connected with the first input-output terminal 1 and thesecond input-output terminal 2. Such semiconductor switches are drivenby supplying the anode electrode 7 with positive voltage as well as zerobias outside the active layer 3 by a not-shown bias line via aresistance.

Circuit-wise, as shown in FIG. 9, this configuration is equivalent to aswitching circuit comprising the coplanar lines and diodes, wherein thefirst input-output terminal 1 is connected with one end of the signalline of the first coplanar line 9, and the anode of the first diode 13is connected with the other end of the signal line of the first coplanarline 9, and the second input-output terminal 2 is connected with one endof the signal line of the second coplanar line 11, and the anode of thesecond diode 14 is connected with the other end of the signal line ofthe second coplanar line 11, and further, to and between the first diode13 and the second diode 14 plural coplanar lines and plural diodes arealternately connected in series. Incidentally, in the presentembodiment, each coplanar line comprises the configuration that thesignal line is sandwiched by conductor connected with the earth, andeach diode is a distributed parameter diode, and its cathode isconnected with the earth.

For the purpose of cultivating a better understanding on the presentembodiment, an example of the semiconductor switch and the switchingcircuits is introduced hereunder, and is explained in detail withreference to the drawings.

In the present example, the area of the anode electrode 7 was set to10×400 μm, and the distance between the cathode electrode 8 and theanode-electrode 7 was set to 3 μm. In addition, the first input-outputterminal 1 and the second input-output terminal 2 are respectivelyconnected with both the ends of the anode electrode 7, and further, 50 Ωloads are respectively connected with the first input-output terminal 1and the second input-output terminal 2. Incidentally, capacitance withzero bias between the cathode and the anode is 20 fF per 100 μm, and onthe other hand, resistance with forward bias is 4 Ω per 100 μm. Inaddition, entire length of the coplanar line is 400 μm.

In the semiconductor switch according to the present example comprisingsuch configuration, positive voltage (2 V for the present example), andzero bias are supplied to the anode so as to alternate the states of theswitch. That is, when positive voltage is applied to the anode of thesemiconductor switch according to the present example, forward bias isto be given to the diode, an equivalent circuit of which is expressed byresistance, thus the switch can be regarded as a coplanar line with lossin shunt due to conductance. That is, at this time, the switch entersthe OFF state. On the other hand, when zero bias was supplied to theanode of the semiconductor switch according to the present example, anequivalent circuit of the diode is expressed by capacitance, thus theswitch is equivalent to a coplanar line without loss. Accordingly, theswitch enters the ON state.

Frequency characteristics on insertion loss as well as isolation of thesemiconductor switch according to the present example are shown in FIG.10. As understandable with reference to FIG. 10, both of insertion lossand isolation show the same wide band width characteristics as in twoexamples respectively in correspondence with the aforementioned firstand second embodiments. In addition, insertion loss at 114.0 GHz is 1.6dB, and isolation is 79 dB. That is, it can be easily understood thatthe semiconductor switch according to the present example is the onewhich has realized high isolation of around 80 dB, maintaining lowinsertion loss, which was conventionally hardly successful in realizingin high frequencies not less than 60 GHz.

FIG. 11 is a graph showing frequency characteristics on insertion lossas well as isolation of the semiconductor switch according to the otherexample in correspondence with the third embodiment. In the presentexample, the area of the anode electrode 7 was set to 10×400 μm, and thedistance between the cathode electrode 8 and the anode electrode 7 wasset to 2.5 μm. In addition, the first input-output terminal 1 and thesecond input-output terminal 2 are respectively connected with both theends of the anode electrode 7, and further, 50 Ω loads are respectivelyconnected with the first input-output terminal 1 and the secondinput-output terminal 2. Capacitance with zero bias between the cathodeand the anode is 20 fF per 100 μm, and on the other hand, resistancewith forward bias is 3.3 Ω per 100 μm. In addition, entire length of thecoplanar line is 400 μm.

In the semiconductor switch according to the present example comprisingsuch configuration, unlike the foregoing example, the case wherealternation of ON and OFF of the switch is conducted by way of applyingboth positive and negative electric power to the anode is examined. Forexample, the switch enters the OFF state with application of 2 V, andthe switch enters the ON state with application of −5 V. Asunderstandable with reference to FIG. 11, both of insertion loss andisolation show the same wide band width characteristics as in theabove-described three examples. In addition, insertion loss at 134.0 GHzis 1.5 dB, and isolation is 85 dB. That is, it can be easily understoodthat the semiconductor switch according to the present example is alsothe one which has realized high isolation of not less than 80 dB,maintaining low insertion loss, which was conventionally hardlysuccessful in realizing in high frequencies not less than 60 GHz.

Incidentally, in each of the above-exemplified examples, it has beenexplained that entire length of the coplanar line is 400 μm, which is ofcourse a mere example, and it goes without saying that the length is notlimited to the 400 μm. This length is one of design parameters to attainnecessary insertion loss as well as isolation. In addition, it goeswithout saying that the present invention is applicable to transmissionlines in general without being limited to coplanar lines.

As explained above, according to the present invention, high isolationof not less than 80 dB is attainable, maintaining low insertion lossalso in high frequencies not less than 60 GHz. This effect is originatedin usage of low-value resistance in the amount of, for example,approximately a half of that for switches using the resistance betweenthe source and the drain in a conventional FET having distributedparameter effect. Perhaps, that is because the distances between theanode and cathode in a diode, and between the gate and the drain as wellas between the gate and the source in an FET can be set shorter than thedistance between the source and the drain in the FET.

Moreover, the above-described first and third embodiments use onlypositive electric power to control the switch and do not need tocomprise negative power supply circuits, which point can be referred toas effective.

1. A semiconductor switch, comprising: a first electrode, a secondelectrode, and a third electrode formed on a semiconductor substrate;said first electrode and said second electrode connected with the earthand are disposed in parallel to each other, said third electrode formedbetween said first and said second electrode; a first terminal coupledto one end of said third electrode; and a second terminal coupled to theother end of said third electrode.
 2. The switch is as claimed in claim1, wherein said first electrode is a drain electrode of a transistor,said second electrode is a source electrode of said transistor, saidthird electrode is a gate electrode of said transistor.
 3. The switch isclaimed in claim 1, wherein said first electrode is a first cathodeelectrode of a diode, said second electrode is a second cathodeelectrode of said diode, said third electrode is an anode electrode ofsaid diode.
 4. (canceled)
 5. A switching circuit, comprising: a coplanartransmission line having a signal line, conductors arranged such thatsaid signal line is sandwiched between the conductors, said conductorsapplied to ground potential; an element having a first electrode coupledto said coplanar transmission line, a second electrode, a thirdelectrode, said second and third electrodes applied to ground potential;and a signal terminal coupled to said coplanar transmission line.
 6. Theswitching circuit is as claimed in claim 5, wherein said first electrodeis a drain electrode of a diode, said second electrode is a sourceelectrode of said diode, said third electrode is a gate electrode ofsaid diode.
 7. The switching circuit is claimed in claim 5, wherein saidfirst electrode is a first cathode electrode of a diode, said secondelectrode is a second cathode electrode of said diode, said thirdelectrode is an anode electrode of said diode.
 8. (canceled)
 9. Theswitching circuit as claimed in claim 5, wherein said first, second, andthird electrode are formed on a substrate including an AlGaAs layer andan InGaAs layer.
 10. A semiconductor switch, comprising: an i-GaAslayer; a first i-AlGaAs layer formed on said first i-GaAs layer; ani-InGaAs layer formed on said i-AlGaAs layer; a n-AlGaAs layer formed onsaid i-InGaAs layer; a first cathode electrode of a diode formed on saidn-AlGaAs layer and supplied with a ground potential; a second cathodeelectrode of a diode formed on said n-AlGaAs layer and supplied withsaid ground potential; an n⁺ GaAs layer formed between said first andsecond anodes on said n-AlGaAs layer; and an anode electrode of a diodeformed on said n⁺ GaAs layer and having a first end coupled to a firstterminal and a second end coupled to a second terminal.
 11. The switchas claimed in claim 10, wherein said diode acts as capacitance when saidground potential is applied to said anode electrode thereby said switchbeing rendered in ON state.
 12. The switch as claimed in claim 10,further comprising: a resistor having a first end connected to saidanode electrode and a second end supplied with said ground potential.13. The switch as claimed in claim 10, wherein each of said anodeelectrode and first and second cathode electrodes are a metal layer. 14.The switch as claimed in claim 10, wherein said anode electrode isprovided to have a Schottky junction with said active region.
 15. Theswitch as claimed in claim 10, wherein said cathode electrodes areprovided to have an ohmic junction with said active region.
 16. Theswitch as claimed in claim 10, wherein said switch is arranged to usefor microwave or millimeter wave.
 17. A switching circuit, comprising: afirst coplanar transmission line having a first signal line and a firstpair of conductors arranged so that said first signal line is sandwichedbetween said first pair of conductors, said first pair of conductorsbeing applied to a ground potential; a second coplanar transmission linehaving a second signal line and a second pair of conductors arranged sothat said signal line is sandwiched between said second pair ofconductors, said second pair of conductors being applied to the groundpotential; and a diode coupled to a signal line coupling said firstsignal line of said first coplanar transmission line and said secondsignal line of said second coplanar transmission line, an anode of thediode being coupled to said signal line and a cathode of the diode beingcoupled to the ground potential.
 18. The switch circuit as claimed inclaim 17, wherein said anode is supplied with a positive voltage so thatthe switching circuit is to be in an off state and is supplied with azero bias so that the switching circuit is to be in an on state.
 19. Theswitch circuit as claimed in claim 17, wherein said switch circuit isarranged to use for microwave or millimeter wave.